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pdsp16350 1 fig. 1 block diagram cordic processor arra y sin co s din mux phase accum register accum scaling register phase offset register phase incr register the pdsp16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit phase accumulator. the more significant bits of this provide 16 bits of phase accuracy for the sine and cosine look up tables. with a 20 mhz system clock, waveforms up to 10 mhz can be produced, with 0.001 hz resolution. if frequency modula- tion is required with no discontinuities, the phase increment value can be changed linearly on every clock cycle. alterna- tively absolute phase jumps can be made to any phase value. the provision of two output multipliers allows the sine and cosine waveforms to be amplitude modulated with a 16 bit value present on the input port. this option can also be used to generate the in-phase and quadrature components from an incoming signal. this i/q split function is required by systems which employ complex signal processing. features direct digital synthesiser producing simultaneous sine and cosine values 16 bit phase and amplitude accuracy, giving spur levels down to - 90 db synthesised outputs from dc to 10 mhz with accuracies better than 0.001 hz amplitude and phase modulation modes 84 pin pga or 132 pin qfp applications numerically controlled oscillator (nco) quadrature signal generator fm, pm, or am signal modulator sweep oscillator high density signal constellation applications with simul- taneous amplitude and phase modulation vhf reference for uhf generators signal demodulator associated products pdsp16256/a programmable fir filter pdsp16510a fft processor pdsp16488a 2d convolver pdsp16350 i/q splitter/nco ds3711 issue 2.3 september 1996
pdsp16350 2 jump mode din19 din21 din23 vdd din26 gnd din28 din30 din32 vout res din17 din18 din20 din22 din24 din25 din27 din29 din31 din33 vin din15 din16 sin15 sin14 din13 din14 sin13 sin12 din11 din12 sin11 sin10 gnd din10 sin9 gnd din9 din8 sin8 sin7 vdd din7 sin6 vdd din6 din5 sin4 sin5 din4 din3 sin2 sin3 din2 din1 sin0 sin1 din0 cos15 cos13 cos11 cos9 cos7 cos6 cos4 cos2 cos0 cen clock gnd cos14 cos12 cos10 vdd cos8 gnd cos5 cos3 cos1 oes oec a b c d e f g h j k l m n fig. 2 a. pin out - bottom view (84 pin pga - ac84)
pdsp16350 3 gc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 sig n/c cen n/c sin0 sin1 sin2 gnd vdd sin3 sin4 n/c sin5 sin6 n/c sin7 sin8 vdd gnd sin9 n/c sin10 sin11 n/c sin12 sin13 sin14 vdd gnd sin15 vin n/c n/c reset gc 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 sig n/c vout din33 gnd vdd din32 n/c din31 din30 n/c din29 din28 n/c din27 gnd vdd din26 din25 din24 din23 vdd din22 gnd din21 vdd din20 din19 gnd vdd din18 mode jump vdd gc 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 sig gnd din17 n/c din16 din15 gnd vdd din14 din13 din12 n/c din11 din10 n/c din9 gnd vdd din8 din7 din6 n/c din5 n/c din4 din3 vdd gnd din2 din1 n/c din0 n/c clk gc 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 sig gnd vdd gnd n/c cos15 cos14 n/c cos13 cos12 n/c cos11 n/c cos10 cos9 vdd gnd cos8 cos7 n/c cos6 cos5 n/c cos4 n/c cos3 cos2 n/c cos1 vdd gnd cos0 oes oec fig.2b pin out (132 pin ceramic qfp - gc132)
pdsp16350 4 signal description din33:0 data bus for the input register. this input register provides a 34 bit, incremental or absolute, phase value, if the mode pin is low. alternatively if the mode pin is high, it provides either an 18 bit phase increment value, via d17:0, and a 16 bit scale value via d33:18 or a 34 bit phase increment value depending on the jump input see below. sin15:0 16 bit sine output data in fractional two? complement format. cos15:0 16 bit cosine output data in fractional two? complement format. cen clock enable for the data input register. when low, data will be latched on the rising edge of the clock. when high data will be retained in the input register. mode mode control input. when low, data in the input register is interpreted as either a 34 bit phase increment value or a 34 bit absolute phase value. when high, the output multipliers are enabled and will scale the waveforms with the upper 16 bits in the input register. the phase increment is loaded from the the lower 18 bits. the full 34 bit phase increment register can also be loaded using jump see below. jump with mode low (frequency or phase modulation) when low jump will allow normal phase incrementing to occur. when high, the data on the input pins will be interpreted as a 34 bit absolute phase value to replace the present value in the accumulator. jump is internally latched to match the delay through the data input register, and to allow data in the internal pipeline to be correctly processed. cen must also be low to latch the required data from din. when mode is high (amplitude modulation) when low jump will allow normal phase incrementing to occur, with the phase increment value taken from the lower 18 data inputs. when high, the data on the input pins will replace the full 34 bits of the phase increment register. cen must also be low to latch the required data. res when high will clear the phase accumulator and phase increment registers, after data in the internal pipeline has been correctly processed. clk input clock. oes output enable for sin 15:0. outputs are high impedance when oes is high. oec output enable for cos15:0. outputs are high impedance when oec is high. vin valid input flag. a delayed version of this input is available on the vout pin, with the delay matching the data processing pipeline delay. this input has no other internal function. vout valid output flag. see above. gnd five ground pins. all must be connected. vcc four +5v pins. all must be connected. table 1. pin description
pdsp16350 5 4) dc can be generated since the increment value can be zero. 5) frequency stability will match the stability of the incoming frequency when the increment is fixed. the residual noise characteristics of an oscillator are very important in modern communication systems. this parameter defines how well the device maintains its set frequency for very short periods (nanoseconds to seconds) of time. poor figures will significantly affect the system signal to noise ratio and limit the dynamic range. the pdsp16350 will, of course, inherit the residual noise characteristics of the source of the incoming frequency. the output frequency is, however, always less than half the incoming frequency in order to satisfy the nyquist criterion. this is in contrast to a phase locked loop synthesiser, when a small input frequency controls a high output frequency. the commonly used 20 log n rule states that the phase noise at the output of a synthesiser will be no better than twenty times the log of the ratio of the output frequency to the input frequency. in a phase locked loop synthesiser n is large, in the pdsp16350 it is less than half. log n is thus less than zero and phase noise improvement is obtained. the output waveforms are produced after a pipeline delay with respect to the din inputs. the effects of the jump or res commands are delayed such that all data in the internal pipe will be processed before the discontinuity occurs. new data may be presented to the device on the cycle following the jump or res and a valid result will be obtained after 31 clock cycles. device operation sine and cosine are simultaneously produced by the cordic processor, which is addressed by the upper 16 bits of the output from a 34 bit phase accumulator. the accumulator divides the digital phase circle into a number of steps, one step for each state of the accumulator. when the accumulator reaches its maximum value it overflows back to zero and the sequence is repeated. the accumulator is incremented once per incoming clock cycle, by an amount which defines the frequency which is to be generated. the increment required is defined by : desired o/p frequency increment = x 2 n incoming clock frequency where n is the number of bits in the accumulator. since the nyquist criteria for proper waveform reconstruction must still be obeyed, the maximum output frequency is half the incom- ing frequency. in practice, when a return is made to the analog world, just meeting the minimum nyquist requirement would require a ?rick wall?low pass filter to remove the alias signals. a more useful ?ule of thumb?is to limit the generated wave- forms to less than 40% of the clock frequency. the resolution, or tuning sensitivity, of the waveform generator is given by : incoming clock frequency resolution = hz 2 n these equations illustrate some very important features of direct digital synthesisers :- 1) tuning sensitivity is defined by both the number of bits in the accumulator and the incoming time base frequency. 2) the oscillator tunes linearly over its entire range. 3) the frequency accuracy matches the accuracy of the incoming increment value. t i n l t pi pi ab device reset apply phase increment first result available c fig. 3 fixed frequency timing diagram
pdsp16350 6 a practical example can be used to illustrate the calcula- tion. with a clock frequency of 10.73864 mhz, and the need to generate an output frequency of 20 khz, then the above equation tells us we need a din value of 31996359. this corresponds to a binary value of: din33:0 = 00 0000 0001 1110 1000 0011 1001 1100 0111 the resolution would be 0.0006 hz. it should be noted that the accuracy of the pdsp16350 cannot be any better than the accuracy of the incoming clock, and these resolutions are based on perfect incoming waveforms. fixed frequency, modulated amplitude the mode pin should be high if modulation of the output waveforms is required. in this mode each of the output waveforms is multiplied by the 16 bit, two s complement, value, present on the most significant 16 bits of the din port. the phase increment register is normally loaded with the 18 bit value on the least significant portion of the din bus. it is also possible to load the full 34 bits of the phase increment register when greater accuracy is required, this is explained below. when using the full 34 bits it is possible to obtain the same frequency resolution as in the fixed amplitude mode described earlier. when using 18 bit accuracy directly from the din bus the correct phase increment value can be calculated as follows : desired o/p frequency din value = x 2 18 clock frequency the frequency resolution is correspondingly reduced and given by : clock frequency resolution = hz 2 18 using the pdsp16350 frequency, phase, and amplitude modulation are all pos- sible with the pdsp16350. the former two requirements are satisfied by the ability to change the phase increment value on every clock cycle. the latter needs the addition of two multipli- ers, which allow both sine and cosine to be modified by an incoming waveform. fixed frequency, constant amplitude to generate sine and cosine outputs at a fixed frequency, the mode pin should be tied low, see fig. 3. the phase increment value required to generate the desired frequency should be clocked into the internal phase increment register. this value is entered via the din port with cen low. if cen subsequently goes inactive (high), the value need not be maintained on the input pins. the correct phase increment value can be calculated as follows : desired o/p frequency din value = x 2 34 clock frequency this will give a decimal value which must be converted to a 34 bit binary number. the frequency resolution of the generated waveforms will be : clock frequency resolution = hz 2 34 with a 20 mhz clock this results in a frequency resolution of 0.001 hz. this can be improved by reducing the clock frequency, with the nyquist restraint being the limiting factor. the latter states that the frequency of the generated waveform must be no more than 50% of the input clock. in practice 40% is a better limit to use, as previously discussed. fig. 4 amplitude modulation (18bit frequency accuracy) n t a b ab device reset apply first data first result available cd c
pdsp16350 7 n t a b ab device reset apply first data first result available c pi apply phase increment 16 bit cordic sin / cos generator a/d converter phase increment value analog data d17:0 d33:18 pdsp 16350 pdsp16256 eprom i q o/p data fig. 6 amplitude modulation (34bit frequency accuracy) fig. 5 iq split function fig. 4 shows the operation of the device when loading the phase increment directly from the din bus. first the device must be reset then data is presented on each clock cycle. the amplitude modulation value is presented on the most signifi- cant 16 bits while the phase increment is presented on the least significant 18 bits. the first valid result is obtained after 31 cycles. (in this mode the least significant 16 bits of the phase increment register remain low). fig.6 shows the operation of the device when using the full 34 bits of the phase increment register. first the device must be reset, then the full 34 bits of the phase increment register are loaded from the din bus by taking signal jump high before the rising edge of the clock. following this new data can be presented on each cycle of the clock. the amplitude modulation value is presented on the most significant 16 bits while the phase increment is presented on the least significant 18 bits. the least significant 16 bits of the phase increment reg- ister remain fixed at the value loaded using jump. the first valid result is obtained after 31 cycles. when using jump to load the phase increment regis- ter, normal operation cannot be maintained. this is because the amplitude modulation value normally presented on the most significant 16 bits of the din bus are replaced by part of the new phase increment value. the am mode is useful in systems requiring frequency sweeps. by varying the ampli- tudes at different frequencies, it is possible to compensate for the analog gain characteristics of amplifiers further along in the system. it can also be used to generate the in-phase and quadra- ture components of an analog waveform, which has been digitized and which is to be processed using complex tech- niques. such a quadrature heterodyning system, alternatively known as an iq splitter, is shown in fig. 5. the output from an a/d converter drives the d33:18 inputs of the pdsp16350. if all sixteen inputs are not required, the unused least significant bits should be tied to ground, and the more significant inputs connected to the a/d converter. multi- plying an input signal with a local oscillator in this manner produces both sum and difference components. the former can be removed by using the pdsp16256 programmable fir filter.
pdsp16350 8 modulated frequency the output frequency can be modulated very simply, see fig 8. since the phase increment value can be loaded as a complete word every cycle, there is no need to provide internal double buffering to prevent spurious frequencies being gener- ated during the load operation. binary frequency shift keyed (bfsk) modulation can easily be implemented by externally multiplexing between two phase increment values represent- ing the two frequencies to be used. the value to be used can be instantaneously changed, thus maintaining phase coher- ence, whilst the bit to be transmitted changes from a mark to a space. frequency hopping could also be simply effected by clocking a new random number into the din port once every thousand cycles, for instance. the output will reflect any change in the frequency after 31 system clock cycles. if the phase increment value on the din port is changed on each clock cycle, then the output frequency will change without introducing any dis- continuities. thus, a linear frequency sweep can be achieved by incrementing the value on the din port by a fixed amount each cycle. al- ternatively, a logarithmic sweep could be implemented by walking a one across the din port. shifting the input one place to the left every hundred cycles, for example, would double the frequency every time. chirp generation for fm - cw radar systems is a typi- cal example of the need for linear frequency sweeps. this application requires the gen- eration of quadrature chirp waveforms and is illustrated in simplified form by fig. 7. one waveform is needed for fig. 8 frequency modulation timing diagram 16 bit cordic sin / cos generator gain compensate rom d17:0 d33:18 pdsp 16350 d/a d/a sin cos sweep generator the transmitter, and the other for the receiver. the phase increment value is supplied by the counter block which simply increments at a rate determined by dividing down the time base clock. the synthesised frequency thus increases during the sweep period. a number of the more significant phase increment bits are used to supply the addresses to a prom. the output of this prom is used to amplitude modulate the sine and cosine waveforms. in this manner it is possible to compensate, at the source, for any poor frequency versus gain characteristics of analog circuits further along in the system. the digital outputs directly drive two d/a converters. once in the analog world, it is necessary to remove the alias frequencies with low pass filters. the phase linearity and pass band ripple characteristics of these filters are very important, if the correct phase relationships are to be maintained be- tween the two waveforms. fig. 7 quadrature chirp generator n t a b ab device reset apply first data first result available c cd
pdsp16350 9 modulated phase relative phase jumps may be made with or without ampli- tude modulation. for example, if a jump of 180 degrees is required, this can be done with a value of : din33:0 = 10 0000 0000 0000 0000 0000 0000 0000 0000 this is loaded into the phase increment register for one cycle, then the normal increment value is re-loaded in the following cycle. alternatively, if no amplitude modulation is needed, an absolute jump to a phase value can be made, see fig. 9. this can be done by activating the jump input during one cycle and also presenting the new phase value at the same time. for example, if a jump to 270 degrees is required : din33:0 = 11 0000 0000 0000 0000 0000 0000 0000 0000 the res (reset) input can alternatively be used if a jump to 0 degrees is needed. this avoids using the din inputs and can be used with or without amplitude modulation. the reset function is internally synchronised to the input clock. fig. 9 phase modulation timing diagram n t a b ab device reset apply first data first result available c cd absolute phase jump absolute phase jump result
pdsp16350 10 characteristic output high voltage output low voltage input high voltage input low voltage input leakage current input capacitance output leakage current output s/c current notes 1. exceeding these ratings may cause permanent damage. functional operation under these conditions is not implied. 2. maximum dissipation or 1 second should not be ex- ceeded, only one output to be tested at any one time. 3. exposure to absolute maximum ratings for extended peri- ods may affect device reliablity. 4. vcc = max, outputs unloaded, clock freq = max. 5. cmos levels are defined as v ih = v dd - 0.5v v il = +0.5v 6. current is defined as positive into the device. 7. the jc data assumes that heat is extracted from the top face of the package. absolute maximum ratings (note 1) supply voltage vcc -0.5v to 7.0v input voltage v in -0.5v to vcc + 0.5v output voltage v out -0.5v to vcc + 0.5v clamp diode current per pin i k (see note 2) 18ma static discharge voltage (hmb) 500v storage temperature t s -65 c to 150 c ambient temperature with power applied t amb military -55 c to +125 c industrial -40 c to 85 c junction temperature 150 c package power dissipation 3500mw thermal resistances junction to case jc 5 c/w min. 2.4 - 3.0 - -10 -50 40 max. - 0.4 - 0.8 +10 +50 250 conditions i oh = 4ma i ol = -4ma gnd < v in < v cc gnd < v out < v cc v cc = max units v v v v a pf a ma symbol v oh v ol v ih v il i in c in i oz i sc value typ. 10 characteristic industrial military units conditions min. typ. max. min. typ. max. d33:0 signal setup to clock rising edge 15 - 15 - ns d33:0 signal hold after clock rising edge 4 - 4 - ns cen setup to clock rising edge 20 - 20 - ns cen hold after clock rising edge 0 - 0 - ns jump, res setup to clock rising edge 10 - 10 - ns jump hold after clock rising edge 6 - 6 - ns res hold after clock rising edge 8 - 8 - ns clock rising edge to output valid 5 30 5 30 ns 30pf clock freq dc 20 dc 20 mhz clock high time 15 - 15 - ns clock low time 20 - 20 - ns oes , oec low to data valid - 20 - 20 ns 30pf oes , oec high to data high impedance - 20 - 20 ns 30pf pipeline delay vin to vout 31 31 31 31 clks vcc current (cmos inputs) - 430 - 450 ma see note 4 vcc current (ttl inputs) - 460 - 500 ma see note 4 switching characteristics electrical characteristics operating conditions (unless otherwise stated) commercial: t amb = 0 c to +70 c t j(max) = 95 c v cc = 5.0v 5% ground = 0v industrial: t amb = -40 c to +85 c t j(max) = 110 c v cc = 5.0v 10% ground = 0v military: t amb = -55 c to +125 c t j(max) = 150 c v cc = 5.0v 10% ground = 0v static characteristics
pdsp16350 11 ordering information industrial (-40 c to +85 c) pdsp16350 / b0 / ac (20mhz - pga) pdsp16350 / b0/ gc (20mhz - qfp) military (-55 c to +125 c) pdsp16350 / a0 / ac (20mhz - pga) pdsp16350 / a0/ gc (20mhz - qfp)
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